1. Field of the Invention
The present invention relates to an exposure method in photolithography for forming a fine pattern in a semiconductor device such as a semiconductor integrated circuit, and further to a semiconductor device and a manufacturing method thereof using the exposure method.
2. Description of the Prior Art
To form a pattern of a semiconductor integrated circuit, improvement of the overlap accuracy between mask layers is important. The mask-layer overlap accuracy is determined by many factors, including a mark detection accuracy in the stepper, the distortion of the wafer due to process treatment, and the field distortion of the stepper. Distortion of the photomask serving as the original plate is one of the most important of the above factors. The existing photomask manufacturing method has a mask-pattern position accuracy of approx. .+-.0.07 mm. Therefore, in this case, patterns of two masks which should originally be located at the same position may be formed with a separation of approx. 0.03 mm from each other on a wafer projected with a reduction factor up to 1/5. The net overlap accuracy of mask patterns has been approx. .+-.0.06 mm so far, which is equivalent to 0.12 mm in range. Therefore, the position uncertainty of the mask consumes approx. 1/4 the range.
This problem has been improved so far by improving mask manufacturing accuracy. However, because the position control technique in the mask manufacturing is already very precise, further improvement is expected to be difficult. The present invention is designed to improve the overlap accuracy between plural mask layers in forming a pattern of a semiconductor integrated circuit as stated above.